#3277 [Engine] extend native-IQ prefill dispatch to SM75

本文

This the rebased version of https://github.com/Niko1221/Strata/pull/1581 for the native-IQ prefill part of the PR.
Reopened PR of https://github.com/Niko1221/Strata/pull/3104 as I couldn't use `/reopen`.

## Problem and result

Strata already has fused native-IQ prompt-expert kernels, but on SM75/Turing the
native path only admits the Q2_0/Q2_0 pair. Native expert packs using IQ2, IQ3,
or IQ4 gate/up tensors therefore fall back to the ordinary MMQ prompt path.

This PR adds a separate, manual A/B switch for the additional SM75 format
pairs. On an RTX 2080 Super Max-Q with an IQ3_XXS pack, enabling the extension
on top of the same [VRAM-loan configuration](https://github.com/Niko1221/Strata/pull/3105) increased median prefill from 774.8
to 859.4 tokens/s (+10.9%). Median generation remained 30.9 tokens/s.

The default path is unchanged when the new switch is absent.

## Approach

Enable the extension with:

```json
{
  "STRATA_PF_FUSED": "1",
  "STRATA_PF_FUSED_SM75": "1",
  "STRATA_PF_FUSED_NATIVE_SM75": "1"
}
```

`STRATA_PF_FUSED` and `STRATA_PF_FUSED_SM75` already exist. This PR introduces
only `STRATA_PF_FUSED_NATIVE_SM75`; it is deliberately separate so existing
SM75 users who enabled the Q2_0 path do not silently opt into new arithmetic.
`STRATA_PF_FUSED_NATIVE` remains the existing global native-path A/B disable.

| Variable | Status |
| --- | --- |
| `STRATA_PF_FUSED` | Existing upstream fused-expert opt-in; still required |
| `STRATA_PF_FUSED_SM75` | Existing upstream SM75 Q2_0 opt-in; still required |
| `STRATA_PF_FUSED_NATIVE` | Existing upstream native-path A/B disable; unchanged |
| `STRATA_PF_FUSED_NATIVE_SM75` | New manual gate for the additional SM75 IQ formats |

The new SM75 coverage is:

- Gate/up: IQ2_XXS, IQ2_XS, IQ2_S, IQ3_XXS, IQ3_S, and IQ4_XS.
- Down: Q2_0 and IQ4_NL.

Admission checks the actual CUDA capability, the specific format pair, and
kernel occupancy. The admitted SM75 formats use the qualified 128-row Turing
shape. Unsupported pairs continue through MMQ. SM80+, SM120, HIP, and decode
dispatch are unchanged.

The path keeps the same selected experts, routing weights, and weighted scatter
order. It does change prompt expert arithmetic and may therefore change prompt
state or generated tokens slightly; it is not claimed to be bit-identical to
MMQ.

The implementation updates the SM75 capability description, native-IQ public
contract and CUDA dispatch in `include/strata/core/sm75_series.hpp`,
`include/strata/prefill/moe_fused_iq.hpp`, and
`src/prefill/moe_fused_iq.cu`. The corresponding format matrix is covered in
`tests/cuda/prefill_fused_iq_test.cpp`, and `docs/DETAILS.md` documents the new
manual gate.

## Validation

Tested revision: `44500122`, based on upstream `e88ee39d` (0.2.0-beta). The
combined end-to-end build used the same native commit plus the separate
[VRAM-loan branch](https://github.com/Niko1221/Strata/pull/3105) at `db02a533`.

### Passed

- Windows Release CUDA build with CUDA 13.4, MSVC 19.51, and SM75 SASS:
  `strata.exe` and `prefill_fused_iq_test.exe`.
- The focused native-IQ CUDA suite passed on the RTX 2080 Super Max-Q for every
  admitted gate/up and down pair listed above, plus the existing Q2_0/Q2_0
  pair. In its reference cases, fused-versus-MMQ relative RMS was
  `3.5e-5`--`4.0e-4`; the large timing cases also passed, with relative RMS
  `1.2e-4`--`2.1e-4`.
- Three fresh-engine end-to-end runs per configuration, serialized on the same
  machine. The production server was stopped during each run and restored
  afterward.
- With every new flag absent, the combined rebased binary measured 513.6 PP
  median versus 514.6 PP for the exact upstream binary (-0.2%, within the run
  ranges), with the same 2,304/226 plan.

### Failed

- The repository-wide test build did not complete on Windows because current
  upstream `src/kernels/gdn_chunk_parity.cpp` calls POSIX `setenv`. The
  production and focused native-IQ targets compile and run; that unrelated
  current-main test compile failure remains.

### Not run

- HIP and SYCL builds.
- Other GPU generations and multi-GPU configurations.
- Full visible-answer parity: the throughput requests reached their 256-token
  reasoning cap, so these runs validate execution and rates, not complete
  answer equivalence.

## Benchmark configuration

- GPU: NVIDIA GeForce RTX 2080 Super Max-Q, 8 GiB, 105 W, compute capability
  7.5.
- CPU/RAM: Intel i7-10875H, 64 GiB RAM.
- PCIe host-to-device probe: approximately 12.2--12.3 GB/s.
- Windows, CUDA 13.4, MSVC Release build with SM75 SASS.
- Model: Qwen3.8-Flash-Next IQ3_XXS native GGUF plus IQ3_XXS expert pack.
- Runtime: 65,536 context, Q4_0 KV, 24,576 resident KV cells, MTP `--spec 4`,
  `--short-read 0`, experimental speed projection, `STRATA_BF16_TC=1`, and
  `STRATA_PROMPT_ATTN_Q4_TC=1` held constant.
- Request: 31,258 fresh prompt tokens, 256 generated tokens, fresh process for
  every repetition. Values below are medians of three engine timing lines.

## Results

| Configuration | Prompt chunk / ring | PP median (range) | TG median (range) |
| --- | ---: | ---: | ---: |
| [VRAM loans](https://github.com/Niko1221/Strata/pull/3105), SM75 native-IQ extension off | 5,376 / 227 | 774.8 (772.7--779.9) | 30.9 (30.2--31.9) |
| Same configuration, extension on | 4,864 / 512 | **859.4** (859.1--860.5) | **30.9** (30.7--32.6) |

The isolated net effect in this workload is +10.9% PP. This is an end-to-end
feature A/B rather than a kernel-only number: native-IQ changes the supported
expert execution path and the planner admits a different chunk/ring geometry.

The separate [request-scoped VRAM-loan PR](https://github.com/Niko1221/Strata/pull/3105)
is not an algorithmic requirement. It was needed on this 8 GiB configuration
to free enough prefill VRAM for the useful native shape. A larger-memory GPU
may admit the native path without it.

The SM75 native-IQ extension itself is independent of upstream
`--prefill-head-alias` and can be used with it. The separate VRAM-loan PR
rejects head alias because both features manage the native output-head
allocation at the prompt/decode boundary.