#3447 [Engine] CUDA 12.0/12.1: widen the f32 bits by hand in the q36 VDEBUG print

说明

## Problem and result

`__half_as_ushort` and `__float2half` are `__device__` only, so a host function cannot call them, and **CUDA 12.0 and 12.1 reject the call**. This site is still in the tree, so the engine does not build with those toolkits:

```
src/qwen35/q36_engine.cu:1659:  (unsigned) __half_as_ushort(__float2half(t[0]));
error: identifier "__half_as_ushort" is undefined in device code
```

0.1.44.1 fixed the sibling site the same way (ab638a56: "the PR widens the bits by hand, as the BF16 loader next to it does"). This change does the same for this one.

With the change the tree builds with CUDA 12.0 and 12.1.

## Related discussion

none

## Approach

Three lines in `src/qwen35/q36_engine.cu`: read the f32 bits with a `memcpy` and print them, instead of converting to half on the host.

The printed value changes from the half-rounded bits to the f32 bits. It is a debug line (it only runs under `STRATA_Q36_VDEBUG`), and it takes no part in any decision the engine makes.

## Validation

**Passed:**

- The engine builds with CUDA 12.0 (nvcc 12.0.140) for sm_89 and serves requests; the same build without the change fails with the error above.
- The engine's own parity tools pass with the change in place.

**Failed:**

- none observed

**Not run:**

- HIP, SYCL and Metal builds. This file is CUDA-only in our build (`strata_qwen35` is CUDA; the q36 path is excluded for HIP gfx906), and there is no ROCm or Intel toolchain on this machine, so the HIP build of this file was not checked.
- Windows (MSVC) was not tried.

## Limits

- Only the one call site is changed. If the same pattern appears elsewhere in the CUDA sources, it will need the same treatment; this PR does not look for it.
- The debug print now shows the f32 bits, which is what the code around it compares anyway.