#2425 Layer split auto: STRATA_SPLIT_UNIFORM=1 restores the uniform miss cost

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## Opt-in restore of the uniform split miss cost (`STRATA_SPLIT_UNIFORM=1`)

Related to #2418. On x16+x4 asymmetric rigs, auto placement moved off-balance in 0.1.41 (absolute 20 GB/s scaling) and stays off-balance in 0.1.44 (relative rule from a 4x gap catches a 4.2x gap: x4.20). This adds the third option next to `STRATA_SPLIT_LINK_ABS`: no per-link scaling at all (the pre-0.1.41 objective). Default off — placement, resident sets and the log lines are byte-identical to main unless set.

**Change** (`src/program/generate.cpp`, +5/−1): read `STRATA_SPLIT_UNIFORM`; when `=1`, force every stage's `link_scale` to 1.0 after `split_rules::link_miss_scale`. Probing/logging untouched. `split_rules::link_miss_scale` itself unchanged, so `split_rules_test` is unaffected.

**Evidence** (dual RTX 3090, x4 second card, IQ3_S 262K, `--pcie-frac 0.35`, same prompts both arms):

| arm | narr | code | 10K | 90K | K |
|---|---|---|---|---|---|
| 0.1.40.3 | 130.86 (CV 8.3%) | 148.22 (CV 3.1%) | 1614.29 (CV 1.4%) | 3416.48 | 27 |
| main default | 114–119 (CV 8–9%) | 135–136 (CV 6–8%) | 1833–1864 | 3097–3144 | 31, x4.20 |
| main + `as_given` + `STRATA_SPLIT_UNIFORM=1` | 132.93/132.20 (CV 7–10%) | 145.29/142.65 (CV 4–7%) | 1567.76/1615.40 (CV 0.4–2.3%) | 3297.84/3281.34 | 27, x1.00 |

Two benches each side, K=27 `x1.00` lines confirmed in the log. Full write-up with the v0.1.41 A/B (iso6/iso7/iso8/iso9, incl. the pcie-frac 0.90 re-measure) is in #2418.