#3499 [Engine] hip: STRATA_SELECT_GRID=2 - the selection scorer's CTA order swaps for L2 (bitwise identical)

Descripción

Problem and result: The WMMA scorer's launch order put all the key tiles of query-tile 0 first: each of the 16 query-tiles re-read the pooled key array from DRAM because L2 (8 MiB) could not hold it between their turns. With STRATA_SELECT_GRID=2 the grid's dimensions swap so the CTAs that share a key tile run together and L2 holds it for all of them. The output is bitwise identical (only the scheduling order of independent CTAs moves).

Related discussion: #3164 (the original PR, closed in the 0.2.0 tracker reset; the check passed but GitHub would not reopen it). Independent of #1749 (wide top-k) and SPLIT2 (#3498) — they optimize different stages of the same pipeline.

Approach: Template parameter bool XQ mapping blockIdx to query/block tiles; opt-in env STRATA_SELECT_GRID=0|1|2 with adaptive threshold STRATA_SELECT_GRID_MIN (default 8192 blocks = 32K context). Default 0 = unchanged. One file changed: src/kernels/cuda/qsa_select.cu (+26/-4).

Validation:
  Passed: Kernel benchmark (v0.2.1.3 @ c093ac26, gfx1151 Radeon 8060S Strix Halo, ROCm 10.1, Linux 7.0.0-38-generic): qsa_select_bench at 32768/262144/524288 context, 256 queries, 5 reps — scorer 0.818/8.429/13.316 ms (old order) vs 0.756/7.831/10.669 ms (swapped), 1.08x/1.08x/1.25x. Ids bitwise identical 256/256 at all depths (qsa_select_bench gate). Engine interleaved 2 rounds at 262144/524288: 1002.8/928.1 tok/s (mainline) vs 1014.1/944.1 tok/s (+grid), +1.1%/+1.7% at depth.
  Failed: none.
  Not run: CUDA backend (kernel is HIP-only); gfx12 hardware (maintainer's R9700 can verify); shallow-context regression below 8192 blocks (the adaptive threshold prevents the swap there by design).

Limits: HIP only; requires STRATA_SELECT_WMMA=1; the engine effect is depth-dependent (strongest at 512K+ where the selection cost is highest).