#3471 [Other] 3× V100-SXM2-16G on PCIe adapters (48 GB) + AVX-only E5 v2: which build path and split for IQ3_S?

Description

### Hardware (verified with `lscpu` / `nvidia-smi` on the actual machine)

| Item | Value |
|---|---|
| CPU | 2× Xeon E5-2697 v2 (Ivy Bridge-EP, 24C/48T) — **AVX only, no AVX2** |
| RAM | 7× 64 GB DDR3L @ 1066 MT/s (448 GB, ~60 GB/s, 2 NUMA nodes) |
| Board | Supermicro X9DRi-LN4F+, 4× PCIe 3.0 x16, Above 4G Decoding available |
| GPU | 3× **Tesla V100-SXM2-16GB** on **SXM2→PCIe adapter boards**, PCIe Gen3 x16, 48 GB total |
| GPU clocks | `clocks.max.memory = 877 MHz` on all three (the standard SXM2 bin, not the 1107 MHz HP variant), SM 1530 MHz, ECC on |
| GPU power | VBIOS reports 300 W; running capped at `-pl 180 -pm 1` (adapters only provide 8-pin + slot power) |
| Storage | 2 TB SATA SSD, no NVMe |
| OS | Ubuntu 24.04, driver 580.178.04, CUDA 12.x toolchain |

The unusual parts are the **three-way 16 GB split** (48 GB total, no NVLink, three equal cards on PCIe) and the **AVX-only host CPU**, which has no AVX2 fallback for the CPU expert pool.

### What I already read before filing

I searched the tracker rather than opening another duplicate. Related threads I read:
`#3411` (measured V100 defaults draft), `#1508` (2× V100-PCIE-32GB community report), `#3283` (sm_70 IQ4_NL layout), `#101` (sm_70 builds, closed), `#1647` (V100 Volta community report, closed), `#2793` (RTX 3060 on an AVX-only E5-2630 v2, open), `#1584` (docker AVX/SSE4.2 fallback, closed), `#2845` / `#1879` / `#1561` (SXM2 16 GB community reports, closed), `#2052` (asymmetric multi-GPU defaults, open), `#1154` (three-GPU two-window pipeline on 3× P4, closed), `#1401` (sm_70 prompt experts on FP16 tensor cores, closed).

None of them covers three 16 GB cards on one host, so I am asking rather than assuming.

### Questions

1. **Build path.** Is the experimental AVX-only build for `sm_70` still the supported route on current releases, or has it been superseded? `#101`/`#1584` suggest it works; I want to confirm it is still the intended path before spending a day compiling the wrong thing. Are there flags beyond `--cuda 12` that matter on an AVX-only host?

2. **Split for IQ3_S at 48 GB.** IQ3_S is ~55 GB plus the ~28.8 GB n-gram table. On three *equal* 16 GB cards, what `--layer-split` and `--resident-budget-gib` do you recommend? `#2052` warns the default multi-GPU recommendation is poor for asymmetrical GPUs — ours are symmetrical, so is an even 1/3 split the right answer, or is a 2+1 window better given PCIe x16 for all three?

3. **Three-GPU pipeline.** `#1154` implemented a three-GPU two-window pipeline for 3× P4 (8 GB each, 24 GB total). Does that path still apply to 3× V100-16G, and is it selected automatically or by flag?

4. **SXM2 on PCIe adapters.** Any known issues when running SXM2 modules through PCIe adapter boards (no NVLink, no display output, 8-pin + slot power only, capped at 180 W)? I have read the Pascal/older-GPU notes; this is a Volta variant of the same question.

### What I will contribute back

The machine is being rebuilt with a clean OS right now; the benchmark harness has not run on this exact hardware combination yet. Once it does I will post a comment in this issue with measured decode/prefill for this config (IQ3_S, 262144 context, MTP, `-pl 180`), so the numbers land in the same thread. I am not going to quote projected numbers as if they were measurements.