#2231 HIP gfx1100: bit-exact decode and prompt-path speedups (+12% decode, KL 0)

Descrição

Bit-exact speedups for HIP on gfx1100 (RX 7900 XTX), measured with `tools/strata_bench.py --long` against same-day upstream main `a0116b27`. Every change keeps the output identical: teacher-forced KL against upstream main at the same expert slot count is **0.0000, 100.0% same top-1, PPL 4.442 / 4.442** over 2,557 positions (16K / 16K / 64K prompts, verify-window decode). Changes that alter numerics (the Q8_0 hyper-connection read from BF16 packs, dropping the BF16 hc copies) are left out of this PR.

## Results (RX 7900 XTX, Ryzen 7 9800X3D, 62.4 GiB, Linux, ROCm 10.2, Qwen3.8-Flash-Next IQ3_S)

Alternating rounds; each cell is the median of 3 runs. Full reports, `results.json` and engine log excerpts are in `bench/results/2026-10-13-community-rx-7900-xtx-gfx1100-exact-speedups/`.

| test | upstream r1 | upstream r2 | PR r1 | PR r2 | PR defaults-only | PR vs upstream |
| --- | ---: | ---: | ---: | ---: | ---: | ---: |
| chat decode tok/s | 84.8 | 88.7 | 96.5 | 97.3 | 92.3 | **+11.7%** |
| 4K prompt tok/s | 1049.0 | 1088.8 | 1118.0 | 1117.0 | 1116.6 | +4.5% |
| 16K prompt tok/s | 1360.5 | 1401.1 | 1427.1 | 1425.3 | 1426.3 | +3.3% |
| 32K prompt tok/s | 1421.7 | 1420.6 | 1445.6 | 1442.5 | 1444.8 | +1.6% |
| agent turn first token (s) | 3.97 | 3.82 | 3.75 | 3.75 | 3.73 | -3.7% |
| agent decode tok/s | 94.1 | 99.1 | 105.2 | 115.7 | 107.7 | **+14.3%** |

Every PR round beats every upstream round in each row. "PR defaults-only" = the PR build without the seven opt-in env switches below, i.e. what a user gets without changing their config. Both engines were built with the same CMake options (`gfx1100`, `-DSTRATA_HIP_EXP_LAYOUTS -DSTRATA_HIP_MMVQ_IL`) and run with the same config, no control vector.

## What changes

**On by default** (each is bitwise the old path; `=0` turns it off):
- `STRATA_ROUTE_FAST`: router lane exchanges as DPP moves; the MoE input copied to the host by the router GEMV's blocks
- `STRATA_GDN_NORM128`: GDN output norm with its one working row group and DPP exchanges (9.3 → 2.0 µs a layer)
- `STRATA_GRUP_WIDE`: the hyper-connection read's up kernel with 512 threads for 1-6 tokens
- `STRATA_TOPK_REGKEYS`, `STRATA_TOPK_SCAN`: QSA top-k keys in registers; serial scans as block scans
- `STRATA_MTP_SELECT_WIDE`: the drafter's row select over 40 blocks (12 → 2.2 µs)
- `STRATA_WAIT_COPY256`: the expert plan read over PCIe by 256 threads
- `STRATA_MULTI_BLOCK_ARGMAX` on HIP (was CUDA-only): 12.0 → 6.0 µs a call
- `STRATA_ADAPT_COPY2`: adaptive-tier swap copies over two DMA streams
- `STRATA_DMA_FLAG_WRITE` (HIP): the PCIe share's landed flag written by the copy stream (`hipStreamWriteValue32`, 6.7 µs) instead of a host function (15 µs)
- `STRATA_DQ_FAST` (Q6_K / IQ4_XS dequant by warps), `STRATA_SCAN_UNROLL` (argmax / top-probability scans), `STRATA_ATTN_MERGE_BOUND` (the drafter's attention merge stops at the last filled chunk)

**Opt-in** (env `=1`): `STRATA_WAIT_FUSE`, `STRATA_MMVQ_IL_PLAIN` (needs `-DSTRATA_HIP_MMVQ_IL`), `STRATA_COMBINE_HITS`, `STRATA_ROUTE_PUB`, `STRATA_WAIT_COMBINE`, `STRATA_PF_LEAN_ISSUE`, `STRATA_PF_COPY2`. Also opt-in and neutral here: `STRATA_GR_FUSE`, `STRATA_DOWN_SWIGLU`, `STRATA_PCIE_FORK`, `STRATA_ADAPT_LAYERWAIT`, `STRATA_GRUP_PF`. Test knobs: `STRATA_EXPERT_SLOTS_MAX`, `STRATA_ATTN_PRE75_NC`.

**Fix:** with `STRATA_MMVQ_IL_PLAIN`, the 32-column hc up kernel (which does not write the interleaved `q8_il` copy) is skipped. Otherwise the attention projections read a stale copy and replies stop after one token. Without the interleaved copy the kernel choice is unchanged.

## How it was checked
- KL: `--pcie-frac 0 --adapt-swaps 0`, the same arguments for both engines, 7,229 expert slots on both; upstream against itself also gives 0.0000 (`kl-teacher-forced.txt` in the results folder).
- Each change was also checked individually during development with a deterministic serve harness (same drafts and text hashes) and kernel-level random-input harnesses for the selection kernels.

## Not tested
- **CUDA and SYCL builds** (no NVIDIA or Intel GPU here). The new HIP-only code (DPP / `permlanex16`, `hipStreamWriteValue32`) is guarded by `__HIPCC__` / `STRATA_USE_HIP`, but the shared `.cu` files were not compiled for CUDA. A CUDA build check before merge would be appreciated.
- Other AMD architectures (gfx906, gfx12, RDNA2).
- The single-request suite only; `--clients N` was not run.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

https://claude.ai/code/session_01C7reiTEKuDUMACf5SbbKbt