#1699 pool_tasks_test and q2_bitplane_parity SIGILL on CPUs without AVX2 (act_quant_any/q2_rows_any have no AVX1 rung)

Description

## Repro

Xeon E5-2470 v2 (Ivy Bridge: SSE4.2 + AVX, no AVX2), v0.1.41 (fb58e0d), built with `STRATA_ISA_FLOOR=avx` and `STRATA_BUILD_TESTS=ON`:

```
$ ./pool_tasks_test                       # no args
Illegal instruction (core dumped)
$ STRATA_Q2_BITPLANE=1 ./q2_bitplane_parity
Illegal instruction (core dumped)
```

Both are registered in CTest (`pool_tasks_test` CMakeLists:1231, `q2_bitplane_parity` :1477), so `ctest` fails on any machine without AVX2.

## Where

```
Program received signal SIGILL, Illegal instruction.
#0 strata::kernels::cpu::act_quant_q8_1_avx2(float const*, int, ActQ&)
#1 main[cold]
```

Reached through the dispatchers in `src/kernels/cpu/expert_layout.cpp` (350-358): `q2_rows_any` and `act_quant_any` know only two rungs - AVX-512 and AVX2 - and the `else` branch has no AVX2 check, so an AVX-only CPU is handed AVX2 code:

```cpp
void act_quant_any(const float* x, int n, ActQ& a) {
    if (cpu_avx512_ok()) act_quant_q8_1(x, n, a);
    else act_quant_q8_1_avx2(x, n, a);          // <- traps on an AVX1 CPU
}
```

`q2_bitplane_parity` also calls `act_quant_q8_1_avx2` directly (q2_bitplane_parity.cpp:46,85).

## Blast radius

The engine itself is safe: a canonical Q2_0 pack on such a CPU exits at `cpu_require_expert_support()` before any of this runs. So this is test-path only - but it hits exactly the users the ISA-floor work (#394) targets: older Xeons building from source with tests enabled. (Found while testing #1697; that PR does not touch these paths.)

## Fix shape

Either gate the two tests like `native_expert_parity` does (skip with a message when `!cpu_avx2_ok()`), or give `act_quant_any`/`q2_rows_any` a third rung - #1697 adds the AVX1 activation quantizer for Q8_K (`q8k_quant_avx1`); the permuted Q8_1 `ActQ` form would need its own AVX1 copy.