#2606 docs: three MI50 notes from #1926 (tail skip on a gfx906 build, IO prefetch with the experts in RAM, Q8_PACKED on gfx906)

Descripción

The docs part of #1926 (points 1-3; point 4, `--dump-logits`' help text, is a code change and is left alone).

**What it changes**, each with the reporter's numbers (Instinct MI50 32 GB, gfx906, engine 0.1.42, UD-IQ4_XS, `--kv k8v4`, single GPU):
- `docs/DETAILS.md`, route tail skip: a gfx906 build (`-DSTRATA_HIP_GFX906=ON`, the CUDA code through HIP) does not define `STRATA_USE_HIP` for the engine, so `decode_defaults_arch_ok()` returns true and the default is on there (the MI50 printed `STRATA_ROUTE_TAIL_SKIP=7 is ON (default)` at 12 of 12 starts). The "other AMD parts are unchanged" sentence and the "not applied ... on HIP and SYCL builds" list now say so (and name the RDNA4 exception the list missed).
- `docs/DETAILS.md`, `STRATA_IO_PREFETCH`: on a 128 GiB host (`--resident-budget-gib 76`) it read nothing ahead (`io prefetch: 0 read ahead` in 4 of 4 requests; the OS read 998.5 MB from the drive for 42,282.7 MB of expert reads).
- `docs/STRIX_HALO.md`, the gfx1151 defaults: the decode switches do not carry over to every AMD card; on the MI50 `STRATA_Q8_PACKED=1` was no faster (23.4 against 23.8 ms per step, 10 interleaved runs, inside the spread), took 1,912.5 MiB more VRAM, and the output was bit-identical.

**What it leaves alone.** All code, including the stale comment above `decode_defaults_arch_ok()` ("gfx906 ... keeps its earlier behaviour"), which an engine PR should fix; every other line.

**How it was checked.** Against #1926, `generate.cpp`'s default and `decode_defaults_arch_ok()`, and `CMakeLists.txt` / `cmake/hip_backend.cmake` (where `STRATA_USE_HIP` is defined). A sub-agent reviewer checked it; its corrections (the build wording, the "not applied" list, the prefetch numbers instead of an inference) are in.

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