#2577 docs: INTEL.md and A770_SPEED_SPEC.md name the SYCL switches the code reads

Descripción

**What it changes.** Two switch names in the Intel docs that the SYCL code does not read:
- `docs/INTEL.md` listed `STRATA_PLAN_PARALLEL=0` among the switches back to the old paths. That run-time switch left the port in the 0.1.40.1 re-migration (23a38a0b removed `plan_parallel()`); the one-thread plan kernel is now the build define `STRATA_PLAN_LOCAL=0` (`sycl/src/kernels/cuda/verify_kernels.dp.cpp`: "0: the original one-thread plan kernel (A/B)").
- `docs/A770_SPEED_SPEC.md` gave the grouped-expert lane count's build define as `-DSTRATA_SYCL_EXPERT_LANES=...`; `iq_kernels.dp.cpp` reads `STRATA_EXPERT_LANES`, which is also the section's own heading.

**What it leaves alone.** Every measurement, and the spec's other historical names (switches described there as parked, local or never merged).

**How it was checked.** A sweep of all 286 `STRATA_*` names in the README, SECURITY.md and docs/ against the code (src, include, serve, setup.py, tools, sycl, metal, cmake, scripts): 279 are read by the code; of the 7 that are not, these two are presented as live switches, and `git log -S` shows where `STRATA_PLAN_PARALLEL` went. No code changes, so no build.

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